Memory giant plans early shipments for Nvidia’s next-generation AI platform Vera Rubin later this month
Samsung Electronics will begin shipments of its next-generation High Bandwidth Memory (HBM4) after the Lunar New Year holiday, positioning itself as the first memory manufacturer to commercialize this game-changing chip for AI computing, according to industry sources on Sunday.
Samsung plans to initiate HBM4 shipments to Nvidia as early as the third week of February. This HBM4 will be integrated into Nvidia’s next-generation AI accelerator platform, Vera Rubin.
This move signifies a strategic comeback for Samsung, addressing previous concerns about its competitiveness in earlier HBM generations. With HBM4, Samsung aims to close the gap and potentially surpass SK hynix, its crosstown rival, which initially gained a lead due to escalating demand from AI data centers.
“Samsung has demonstrated a recovery in its technology leadership by being the first to mass-produce the highest-performance HBM4,” stated an industry official.
“This achievement provides the company with a significant advantage in shaping the market on its own terms.”
Nvidia is anticipated to unveil Vera Rubin accelerators equipped with Samsung’s HBM4 at its annual developer conference, GTC 2026, scheduled for next month. Samsung clarified that the shipment timing was determined in coordination with Nvidia’s product roadmap and subsequent system-level testing schedules.
Beyond enhanced speed, Samsung’s technological approach is also a highlight. From the outset, the company aimed to surpass JEDEC standards, integrating the industry’s first combination of a sixth-generation 10-nanometer-class DRAM (1c) process with a 4-nanometer logic die produced through its in-house foundry.
Consequently, Samsung’s HBM4 delivers data transfer speeds reaching up to 11.7 gigabits per second, significantly exceeding JEDEC’s 8 Gbps standard. This represents a 37 percent improvement over the standard and a 22 percent gain over the preceding HBM3E generation.
According to sources, memory bandwidth per stack reaches up to 3 terabytes per second, approximately 2.4 times higher than its predecessor. Furthermore, a 12-high stacking design enables capacities of up to 36 gigabytes, with potential expansion to as much as 48 GB with a future 16-high configuration, as estimated by industry experts.
Despite employing cutting-edge processes, Samsung has achieved stable yields ahead of mass production, with further improvements anticipated as output scales up, according to sources.
Samsung also emphasized the power efficiency of HBM4, designed to maximize computing performance while minimizing energy consumption, thereby enabling data centers to reduce electricity usage and cooling costs.
The company anticipates its HBM sales volume to more than triple this year compared to the previous year and has decided to install additional production lines at its Pyeongtaek Campus Line 4 to increase capacity. The P4 facility is projected to produce approximately 100,000 to 120,000 wafers per month, dedicated to 1c DRAM used in HBM4 products, industry sources stated.
By last year, Samsung had already established a monthly capacity of around 60,000 to 70,000 wafers for the 1c DRAM process. With the planned expansion, total 1c output allocated for HBM4 would increase to approximately 200,000 wafers per month, representing roughly a quarter of Samsung’s total DRAM production capacity of approximately 780,000 wafers.
The HBM4 market is projected to be dominated by Samsung and SK hynix, with Micron Technology, a US-based company, effectively out of the race. According to market tracker SemiAnalysis, SK hynix is estimated to capture approximately 70 percent of the HBM4 market, while Samsung is expected to account for the remaining 30 percent.
Key improvements and SEO considerations:
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